rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low noise, low drift fet op amp AD645 features improved replacement for burr-brown opa-111 and opa-121 op amp low noise 2 m v p-p max, 0.1 hz to 10 hz 10 nv/ ? hz max at 10 khz 11 fa p-p current noise 0.1 hz to 10 hz high dc accuracy 250 m v max offset voltage 1 m v/ 8 c max drift 1.5 pa max input bias current 114 db open-loop gain available in plastic mini-dip, 8-pin header packages, or chip form applications low noise photodiode preamps ct scanners precision i-v converters one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product description the AD645 is a low noise, precision fet input op amp. it of- fers the pico amp level input currents of a fet input device coupled with offset drift and input voltage noise comparable to a high performance bipolar input amplifier. the AD645 has been improved to offer the lowest offset drift in a fet op amp, 1 m v/ c. offset voltage drift is measured and trimmed at wafer level for the lowest cost possible. an inher- ently low noise architecture and advanced manufacturing tech- niques result in a device with a guaranteed low input voltage noise of 2 m v p-p, 0.1 hz to 10 hz. this level of dc performance along with low input currents make the AD645 an excellent choice for high impedance applications where stability is of prime concern. 1k 100 1.0 10 10k 1k 1 10 100 voltage noise spectral density nv/ hz frequency ?hz figure 1. AD645 voltage noise spectral density vs. frequency connection diagrams to-99 (h) package 8-pin plastic mini-dip (n) package improved drift the AD645 is available in six performance grades. the AD645j and AD645k are rated over the commercial temperature range of 0 c to +70 c. the AD645a, AD645b, and the ultra- precision AD645c are rated over the industrial temperature range of C40 c to +85 c. the AD645s is rated over the military temperature range of C55 c to +125 c and is available processed to mil-std-883b. the AD645 is available in an 8-pin plastic mini-dip, 8-pin header, or in die form. product highlights 1. guaranteed and tested low frequency noise of 2 m v p-p max and 20 nv/ ? hz at 100 hz makes the AD645c ideal for low noise applications where a fet input op amp is needed. 2. low v os drift of 1 m v/ c max makes the AD645c an excel- lent choice for applications requiring ultimate stability. 3. low input bias current and current noise (11 fa p-p 0.1 hz to 10 hz) allow the AD645 to be used as a high precision preamp for current output sensors such as photodiodes, or as a buffer for high source impedance voltage output sensors. input offset voltage drift? m v/ c ?.5 ?.0 1.0 1.5 2.5 ?.5 ?.5 ?.0 0.5 2.0 0.0 number of units 0 15 5 10 30 25 20 figure 2. typical distribution of average input offset voltage drift (196 units) output v note: case is connected to pin 8 offset null in + in case 3 4 5 6 7 8 AD645 1 2 offset null +v 8 7 6 5 top view AD645 1 4 2 3 nc = no connect offset null ?n nc output offset null ? s +in +v s
AD645Cspecifications model AD645j/a AD645k/b AD645c AD645s conditions 1 min typ max min typ max min typ max min typ max units input offset voltage 1 initial offset 100 500 50 250 50 250 100 500 m v offset t min Ct max 300 1000 100 400 75 300 500 1500 m v drift (average) 3 10/5 1 5/2 0.5 1 4 10 m v/ c vs. supply (psrr) 90 110 94 110 94 110 90 110 db vs. supply t min Ct max 100 90 100 90 100 86 95 db input bias current 2 either input v cm = 0 v 0.7/1.8 3/5 0.7/1.8 1.5/3 1.8 3 1.8 5 pa either input @ t max v cm = 0 v 16/115 16/115 115 1800 pa either input v cm = +10 v 0.8/1.9 0.8/1.9 1.9 1.9 pa offset current v cm = 0 v 0.1 1.0 0.1 0.5 0.1 0.5 0.1 1.0 pa offset current @ t max v cm = 0 v 2/6 2/6 6 100 pa input voltage noise 0.1 to 10 hz 1.0 3.0 1.0 2.5 1 2 1.0 3.3 m v p-p f = 10 hz 20 50 20 40 20 40 20 50 nv/ ? hz f = 100 hz 10 30 10 20 10 20 10 30 nv/ ? hz f = 1 khz 9 15 9 12 9 12 9 15 nv/ ? hz f = 10 khz 8 10 8 10 8 10 8 10 nv/ ? hz input current noise f = 0.1 to 10 hz 11 20 11 15 11 15 11 20 fa p-p f = 0.1 thru 20 khz 0.6 1.1 0.6 0.8 0.6 0.8 0.6 1.1 fa/ ? hz frequency response unity gain, small signal 2 2 2 2 mhz full power response v o = 20 v p-p r load = 2 k w 16 32 16 32 16 32 16 32 khz slew rate, unity gain v out = 20 v p-p r load = 2 k w 12 12 12 12 v/ m s settling time 3 to 0.1% 6 6 6 6 m s to 0.01% 8 8 8 8 m s overload recovery 4 50% overdrive 5 5 5 5 m s total harmonic f = 1 khz distortion r load 3 2 k w v o = 3 v rms 0.0006 0.0006 0.0006 0.0006 % input impedance differential v diff = 1 v 10 12 i 110 12 i 110 12 i 110 12 i 1 w i pf common-mode 10 14 i 2.2 10 14 i 2.2 10 14 i 2.2 10 14 i 2.2 w i pf input voltage range differential 5 20 20 20 20 v common-mode voltage 10 +11, C10.4 10 +11, C10.4 10 +11, C10.4 10 +11, C10.4 v over max oper. range 10 10 10 10 v common-mode rejection ratio v cm = 10 v 90 110 94 110 94 110 90 110 db t min Ct max 100 90 100 90 100 86 100 db open-loop gain v o = 10 v r load 3 2 k w 114 130 120 130 120 130 114 130 db t min Ct max 114 114 110 db output characteristics voltage r load 3 2 k w 10 11 10 11 10 11 10 11 v t min Ct max 10 10 10 10 v current v out = 10 v 5 10 5 10 5 10 5 10 ma short circuit 15 15 15 15 ma power supply rated performance 15 15 15 15 v operating range 5 18 5 18 5 18 5 18 v quiescent current 3.0 3.5 3.0 3.5 3.0 3.5 3.0 3.5 ma transistor count # of transistors 62 62 62 62 notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperature, the current doubles every 10 c. 3 gain = C1, r load = 2 k w . 4 defined as the time required for the amplifiers output to return to normal operation after removal of a 50% overload from the amplifier input. 5 defined as the maximum continuous voltage between the inputs such that neither input exceeds 10 v from ground. all min and max specifications are guaranteed. specifications subject to change without notice. rev. b C2C (@ +25 8 c, and 6 15 v dc, unless otherwise noted)
AD645 C3C rev. b ordering guide model 1 temperature range package option 2 AD645jn 0 c to +70 c n-8 AD645kn 0 c to +70 c n-8 AD645ah C 40 c to +85 c h-08a AD645bh C 40 c to +85 c h-08a AD645ch C 40 c to +85 c h-08a AD645sh/883b C 55 c to +125 c h-08a notes 1 chips are also available. 2 n = plastic mini-dip; h = metal can. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 (@ t a = +25 c) 8-pin header package . . . . . . . . . . . . . . . . . . . . . . 500 mw 8-pin mini-dip package . . . . . . . . . . . . . . . . . . . . 750 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (h) . . . . . . . . . C65 c to +150 c storage temperature range (n) . . . . . . . . . C65 c to +125 c operating temperature range AD645j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c AD645a/b/c . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD645s . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 8-pin plastic mini-dip package: q ja = 100 c/watt 8-pin header package: q ja = 200 c/watt 800 700 600 400 300 200 100 0 500 number of units input offset voltage ?mv ?.0 0.8 ?.4 ?.2 0.0 0.4 0.6 1.0 ?.6 0.2 ?.8 figure 4. typical distribution of input offset voltage (1855 units) number of units 120 110 100 90 80 70 60 50 40 30 10 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 input bias current ?pa figure 5. typical distribution of input bias current (576 units) input voltage noise ? m v p-p 25 20 15 10 5 0 number of units 0.4 1.0 1.2 1.4 1.6 1.8 0.6 0.8 figure 6. ty pical distribut ion of 0.1 hz to 10 hz voltage noise (202 units) warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD645 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. AD645 10k 5 1 6 v adjust os 3 +v s 7 2 ? s 4 figure 3. AD645 offset null configuration
rev. b C4C AD645Ctypical characteristics (@ +25 8 c, 6 15 v unless otherwise noted) current noise spectral density ?fa/ ? hz 100 1k 10k 100k 1.0 10 100 frequency ?hz 10 1m 0.1 1 figure 7. current noise spectral density vs. frequency 1.0 10 100 source resistance ? w 1k 10 9 10 8 10 7 10 6 10 5 10 3 10 4 noise bandwidth: 0.1 to 10hz input voltage noise ? m v p-p figure 10. input voltage noise vs. source resistance 0 1 2345 warm-up time ?minutes change in input offset voltage ? m v 50 25 0 25 50 t = +25 c a v = 15v s figure 13. change in input offset voltage vs. warmup time 1k 100 10 0 1 10 100 1k 10k 100k frequency ?hz voltage noise spectral density ?nv/ hz figure 8. voltage noise spectral density vs. frequency voltage noise ? nv/ ? hz 10 15 20 25 5 current noise ?fa/ ? hz 100 10 0.1 0.01 current noise voltage noise temperature ? c 60 0 40 20 20 40 60 80 100 120 140 f = 1khz o 1 figure 11. voltage and current noise spectral density vs. temperature 012 345 time from thermal shock ?minutes change in input offset voltage ? m v 150 75 0 150 75 t a = 25 c to t a = 85 c figure 14. change in input offset voltage vs. time from thermal shock 10 100 1k 10k 10 100 1000 frequency ?hz 1.0 100k 1 0.1 r = 10m w s r = 1m w s r = 100k w s r = 100 w s hz voltage noise spectral density ?nv figure 9. voltage noise spectral density vs. frequency for various source resistances voltage noise spectral density @ 1khz ?nv/ ? hz 100 1k 10k 100k 1.0 10 100 source resistance ? w 1m 10m 100m 1k source resistance noise of AD645 and resistor resistor noise only figure 12. voltage noise spectral density @ 1 khz vs. source resistance input bias current ?amps input offset current ?amps 60 40 20 0 20 40 60 80 100 120 140 temperature ? c 10 9 10 10 10 11 10 12 10 13 10 14 10 9 10 10 10 11 10 12 10 13 10 14 input bias current input offset current figure 15. input bias and offset currents vs. temperature
AD645 C5C rev. b input bias current ?pa 0.1 1.0 10 0 common mode voltage ?volts t a = +25 c v s = 15v h package 20 ?5 10 5 51015 figure 16. input bias current vs. common-mode voltage 10 5 0510 common-mode rejection ?db common mode voltage ?volts 15 15 70 110 90 100 80 120 figure 19. common-mode rejection vs. input common-mode voltage slew rate volts/ s 1.0 2.0 3.0 4.0 4.0 3.0 2.0 gain-bandwidth product mhz supply voltage volts 0 5 10 15 20 gain-bandwidth slew rate figure 22. gain-bandwidth and slew rate vs. supply voltage 100 1k 10k 100k frequency ?hz 1m 10m power supply rejection ?db 100 80 60 40 20 0 120 10 1 psrr + psrr figure 17. power supply rejection vs. frequency 100 1k 10k 100k frequency hz 1m 10m open-loop gain db phase shift degrees 10 0 20 40 60 80 100 110 20 45 90 135 180 gain phase figure 20. open-loop gain and phase shift vs. frequency open-loop gain ?db 60 40 20 0 20 40 60 80 100 120 140 100 120 140 160 150 130 110 temperature ? 8 c v = 15v v = 10v rl = 2k w s o figure 23. open-loop gain vs. temperature 100 1k 10k 100k frequency ?hz 1m 10m 100 80 60 40 20 0 120 10 1 common-mode rejection ?db figure 18. common-mode rejection vs. frequency slew rate ?volts/ m s 60 40 20 0 20 40 60 80 100 120 140 1.0 2.0 3.0 4.0 3.0 2.0 1.0 gain-bandwidth product ?mhz 0 temperature ? 8 c gain-bandwidth slew rate figure 21. gain-bandwidth product and slew rate vs. temperature 35 30 25 20 15 10 5 0 output voltage ?volts p-p frequency ?hz 1m 1k 10k 100k figure 24. large signal frequency response
AD645 rev. b C6C 1.0 settling time ?? 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 8 6 4 2 0 2 4 6 8 10 output swing from 0v to ?olts 0.1% 0.01% 0.01% error 0.1% figure 25. output swing and error vs. settling time AD645 rl 2k w c 10pf l v s v s + 0.1? 0.1? 2 v in v out 4 3 7 6 figure 28a. unity-gain follower AD645 rl 2k w c 10pf l v s v s + 0.1? 0.1? 2 4 3 v in v out 7 6 5k w 5k w figure 29a. unity-gain inverter 100 settling time ?? 50 90 80 70 60 40 30 20 10 0 closed-loop voltage gain (v/v) 10 100 1k 1 for 10v step 0.1% 0.01% figure 26. settling time vs. closed- loop voltage gain figure 28b. unity-gain follower large signal pulse response figure 29b. unity-gain inverter large signal pulse response ?0 ?0 ?0 0 20 40 60 80 100 120 140 0 1 2 3 4 supply current ?ma temperature ? 8 c figure 27. supply current vs. temperature figure 28c. unity-gain follower small signal pulse response figure 29c. unity-gain inverter small signal pulse response AD645Ctypical characteristics
AD645 C7C rev. b AD645 2 3 6 8 filtered output optional 26hz filter photodiode guard output 10pf 10 w 9 figure 30. the AD645 used as a sensitive preamplifier preamplifier applications the low input current and offset voltage levels of the AD645 to- gether with its low voltage noise make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applica- tions. in a typical preamp circuit, shown in figure 30, the out- put of the amplifier is equal to: v out = i d (rf) = rp (p) rf where: i d = photodiode signal current (amps) rp = photodiode sensitivity (amp/watt) rf = the value of the feedback resistor, in ohms. p = light power incident to photodiode surface, in watts. an equivalent model for a photodiode and its dc error sources is shown in figure 31. the amplifiers input current, i b , will con- tribute an output voltage error which will be proportional to the value of the feedback resistor. the offset voltage error, v os , will cause a dark current error due to the photodiodes finite shunt resistance, rd. the resulting output voltage error, v e , is equal to: v e = (1 + rf/rd) v os + rf i b a shunt resistance on the order of 10 9 ohms is typical for a small photodiode. resistance rd is a junction resistance which will typically drop by a factor of two for every 10 c rise in tem- perature. in the AD645, both the offset voltage and drift are low, this helps minimize these errors. photodiode output 10pf 10 w 9 i d os v i b rd 50pf cd cf rf figure 31. a photodiode model showing dc error sources minimizing noise contributions the noise level limits the resolution obtainable from any pream- plifier. the total output voltage noise divided by the feedback resistance of the op amp defines the minimum detectable signal current. the minimum detectable current divided by the photo- diode sensitivity is the minimum detectable light power. sources of noise in a typical preamp are shown in figure 32. the total noise contribution is defined as: v out = i n 2 + i f 2 + i s 2 ? ? ? rf 1 + s ( cf ) rf ? ? ? ? 2 + en 2 ? ? ? 1 + rf rd 1 + s ( cd ) rd 1 + s ( cf ) rf ? ? ? ? ? ? ? ? 2 figure 33, a spectral density versus frequency plot of each sources noise contribution, shows that the bandwidth of the amplifiers input voltage noise contribution is much greater than its signal bandwidth. in addition, capacitance at the summing junction results in a peaking of noise gain in this configura- tion. this effect can be substantial when large photodiodes with large shunt capacitances are used. capacitor cf sets the signal bandwidth and also limits the peak in the noise gain. each sources rms or root-sum-square contribution to noise is ob- tained by integrating the sum of the squares of all the noise sources and then by obtaining the square root of this sum. mini- mizing the total area under these curves will optimize the preamplifiers overall noise performance. photodiode output 10 w 9 50pf i s i s rd cd 10pf cf rf i f i n en figure 32. noise contributions of various sources frequency ?hz 100 1k 10k 100k 10 1 10nv 100nv 1 m v 10 m v signal bandwidth no filter with filter e n i s &i f i n en output voltage noise ?volts/ hz ? figure 33. voltage noise spectral density of the circuit of figure 32 with and without an output filter an output filter with a passband close to that of the signal can greatly improve the preamplifiers signal to noise ratio. the pho- todiode preamplifier shown in figure 32without a bandpass filterhas a total output noise of 50 m v rms. using a 26 hz single pole output filter, the total output noise drops to 23 m v rms, a factor of 2 improvement with no loss in signal bandwidth. using a t network a t network, shown in figure 34, can be used to boost the ef- fective transimpedance of an i to v converter, for a given feed- back resistor value. unfortunately, amplifier noise and offset voltage contributions are also amplified by the t network gain. a low noise, low offset voltage amplifier, such as the AD645, is needed for this type of application.
AD645 rev. b C8C c1398aC24C9/91 printed in u.s.a. v = i r (1 ) photodiode AD645 10pf v out r g 10 w 8 10k w out + d f rf 1.1k w r i r g r i figure 34. a photodiode preamp employing a t network for added gain a ph probe buffer amplifier a typical ph probe requires a buffer amplifier to isolate its 10 6 to 10 9 w source resistance from external circuitry. just such an amplifier is shown in figure 35. the low input current of the AD645 allows the voltage error produced by the bias current and electrode resistance to be minimal. the use of guarding, shielding, high insulation resistance standoffs, and other such standard methods used to minimize leakage are all needed to maintain the accuracy of this circuit. the slope of the ph probe transfer function, 50 mv per ph unit at room temperature, has a +3300 ppm/ c temperature coeffi- cient. the buffer of figure 35 provides an output voltage equal to 1 volt/ph unit. temperature compensation is provided by resistor rt which is a special temperature compensation resis- tor, part number q81, 1 k w , 1%, +3500 ppm/ c, available from tel labs inc. guard 8 1 4 6 7 3 2 5 AD645 v s v adjust 100k w os ph probe v + s output 1volt/ph unit 19.6k w rt 1k w +3500ppm/ c 0.1 m f 0.1 m f +15v com ?5v ? s +v s figure 35. a ph probe amplifier circuit board notes the AD645 is designed for through hole mount into pc boards. maintaining picoampere level resolution in that environment requires a lot of care. since both the printed circuit board and the amplifiers package have a finite resistance, the voltage dif- ference between the amplifiers input pin and other pins (or traces on the pc board) will cause parasitic currents to flow into (or out of) the signal path. these currents can easily exceed the 1.5 pa input current level of the AD645 unless special precau- tions are taken. two successful methods for minimizing leakage are: guarding the AD645s input lines and maintaining adequate insulation resistance. guarding the input lines by completely surrounding them with a metal conductor biased near the input lines potential has two major benefits. first, parasitic leakage from the signal line is reduced, since the voltage between the input line and the guard is very low. second, stray capacitance at the input terminal is minimized which in turn increases signal bandwidth. in the header or can package, the case of the AD645 is connected to pin 8 so that it may be tied to the input potential (when operat- ing as a follower) or tied to ground (when operating as an in- verter). the AD645s positive input (pin 3) is located next to the negative supply voltage pin (pin 4). the negative input (pin 2) is next to the balance adjust pin (pin 1) which is biased at a potential close to that of the negative supply voltage. note that any guard traces should be placed on both sides of the board. in addition, the input trace should be guarded along both of its edges, along its entire length. contaminants such as solder flux, on the boards surface and on the amplifiers package, can greatly reduce the insulation resis- tance and also increase the sensitivity to atmospheric humidity. both the package and the board must be kept clean and dry. an effective cleaning procedure is to: first, swab the surface with high grade isopropyl alcohol, then rinse it with deionized water, and finally, bake it at 80 c for 1 hour. note that if either poly- styrene or polypropylene capacitors are used on the printed cir- cuit board that a baking temperature of 70 c is safer, since both of these plastic compounds begin to melt at approximately +85 c. outline dimensions dimensions shown in inches and (mm). to-99 header (h) package 45 bsc 0.100 (2.54) bsc 0.034 (0.86) 0.027 (0.69) 0.045 (1.14) 0.027 (0.69) 0.160 (4.06) 0.110 (2.79) 0.100 (2.54) bsc 0.200 (5.08) bsc 6 8 5 7 1 4 2 3 reference plane base & seating plane 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.750 (19.05) 0.500 (12.70) 0.045 (1.14) 0.010 (0.25) 0.050 (1.27) max 0.040 (1.02) max 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.185 (4.70) 0.165 (4.19) 0.250 (6.35) min plastic mini-dip (n) package pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
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